ASIC and FPGA

Expertise and versatility, with speedy new-tech mastering.

Our hardware engineering experience for any of your avionics, network communications, DSP and AI/ML, consumer device, automotive, smartphone, multimedia, aerospace, automated test equipment and EDA tool pre-silicon validation/verification projects.
From modeling or specification phase to manufacturing.

First time right

The key to success is the first-time-right method of design and verification that maximizes correct operation of the chip upon product integration. Our advantages are abundance of experience, coding techniques, and verification approach. Independent teams for RTL design and UVM based verification are giving higher confidence in future result. With objective measures providing a clear status and progress reports it is easy to track and react in demanding time-to-market projects.
Our matured processes and comprehensive checklist have enabled us to execute complex RTL designs in different areas. We have also contributed in Verification/Validation processes.

Designing or verifying ASIC, SoC, or FPGA for the product is a challenge in terms of budget, time to market period, and available engineers. Most of our customers have been the biggest semiconductor companies. We offer:

 

  • Architecture/concept design
  • Block/IP level ASIC/FPGA development
  • IP integration
  • ASIC/FPGA simulation
  • ASIC/FPGA verification
  • ASIC/FPGA certification

State-of-the-art tools we use

Examples of our work

Wave Computers

Low latency industrial switch IP, FPGA design.

Key points:

  • 1Gbps ethernet frame processing
  • Redundant frame generation, detection and elimination
  • Low latency system without exceeding specified FPGA resources
  • Multiple FPGA custom platforms implementation
  • IP adaptation for ASIC

Read more in case study.

ASK Industries

Ethernet switch, DO-254 certification

Key points:

  • Requirements-driven process-oriented safety standard used on commercial electronics that go into aircraft (DAL A)
  • Requirements driven UVM verification
  • Code (Statement, Branch, Condition, Expression) and requirement coverage 100%
  • Documentation and tagging (requirements, specification, RTL, tests)

Read more in case study.

Speedata

Dataflow departmental appliance for deep learning, ASIC design.

Key points:

  • Architecture development based on specification
  • Design based on specification – RTL
  • Pre-silicon FPGA prototype
  • Independent verification team
  • SystemC-NS3 model – TLM Cycle based model of the system co-simulation with NS3 network model
  • UVM verification model development

Read more in case study.

Valens

Specman E and UVM SystemVerilog, ASIC verification.

Key points:

  • Requirements or specification-driven process
  • UVM verification environment development
  • VIP definition and design
  • Test generation

Read more in case study.

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