Destructive interference

Active road noise cancelation system, FPGA design and development

Destructive interference

Active road noise cancelation system, FPGA design and development

The customer was ASK Automotive Industries Group. The goal of the project was to create a hardware in the loop (HIL) system for active noise cancellation in a car. The system lowers the noise level by capturing low frequency noise with microphone and reproducing captured noise with 180 degree shifted phase using a bass speaker. Since the system captures low frequency noise, important high frequency sounds like sirens and car horns are still present.

Figure 1. Noise cancelation principle

This active road noise cancelation system consists of an ADC (analog-to-digital converter), a DAC (digital-to-analog converter), FPGA (field-programmable gate array), and a PC. A dedicated ADC integrated circuit samples sound at its input and generates I2S (Inter-IC Sound) packets at its output. I2S is a serial bus interface standard used for connecting digital audio devices. The purpose of a dedicated DAC integrated circuit is to receive the I2S packets and generate sound at its output. The FPGA part of the active road noise cancelation system consists of a configuration module, a receiving (Rx) audio data buffer, a transmitting (Tx) audio data buffer, PCIe (Peripheral Component Interconnect Express) interface, and a filter. A configuration module configures ADC and DAC via I2C (Inter-Integrated Circuit) interface. Rx audio data buffer stores the I2S packets generated by ADC. Tx audio data buffer stores audio data received from the PC via PCIe interface, which are then converted to the I2S packets and sent to DAC. PCIe interface interconnects the host computer with the FPGA Rx/Tx audio data buffers and the filter module. The filter module is a block which processes the stream of input samples (discretized audio signal). It has one input port which takes sample by sample at a specific rate (sample rate). The sample rate of the filter is the same as the sample rate of the ADC and DAC in the system. The filter has also one output port which forwards the filtered sample. Inside the Filter block there is a predefined number of stages. Each stage is calculated as a sum of previous stage value and corresponding sample multiplied by the corresponding coefficient.

Figure 2. Active road noise cancelation system block diagram

The implementation of the HIL system for active noise cancelation in the car was performed in the VHDL hardware description language. Synthesis and implementation were done in Xilinx Vivado Design Suite. The FPGA part of the system was implemented on Xilinx Virtex UltraScale+ development board. ADC and DAC were mounted on separated boards connected with a FMC connector with the FPGA development board. The main challenge was to achieve fixed audio latency from input (ADC) to output (DAC). Linux operating system was used for that purpose.


The project covered the complete development, from the system architecture planning, to ADC/DAC extension board development, to RTL design and verification, to driver development and complete product integration. All the development steps were conducted by RT-RK.

HIL device analog board

HIL device interior

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