The system used multiple high speed ADC inputs running at 4Gsps, increasing the data rate up to 40Gsps.
While evaluating market available hardware to prove and demonstrate the system functionality, it was concluded that neither available FPGA based emulation platform, could fulfill design requirements either due to a small DSP processing power or due to a small number of available IO connections. Thus, the goal of this project was to design and produce R&D platform and to design an FPGA architecture with the required DSP processing.
The system overview and data speed domains are shown below.


The number of the interconnections and required data rates dictated a specially designed and developed backplane.

Key achievements
During this project, in several phases and stages, our team managed to build unique pieces of hardware, beyond the state-of-the-art specifications and industry standards:
- A blade server system with 17 cutting edge FPGA devices running in parallel
- 36 conductive layers design, the 21-inch backplane with total data throughput of 1.6 Tbps (1600+ LVDS interconnections running at 1Gbps)
- High speed differential signaling in ADC input stage up to 6.25 Gbps