RISC-V

RISC-V – a significant shift in the semiconductor industry by providing a free, open, and flexible ISA that encourages innovation and competition. Its adoption is growing across a range of applications, from embedded systems to high-performance computing.

Discover our innovative work in various aspects of optimization and implementation, including enhancing A/V libraries, porting Android 13, and deploying a hypervisor on RISC-V.

For inquiries please contact us at info@rt-rk.com

INTRODUCTION

The RISC-V is an open-source instruction set architecture (ISA) used for the development of custom processors targeting a variety of end applications – from embedded designs to high-performance computing. Originally developed at the University of California, Berkeley, the RISC-V ISA is considered the fifth generation of processors built on the concept of the reduced instruction set computer (RISC). Due to its openness and its technical merits, it has become very popular in recent years.

Significance of RISC-V lies in its key features:

  • Openness: the open-source nature enables collaboration across the community for the continuous improvements and better insight into the codebase and roadmap for the engineers
  • Extensibility: RISC-V ISA is defined as a base integer ISA, which must be present in any implementation, plus optional extensions to the base ISA. Each base integer instruction set is characterized by the width of the integer registers and the corresponding size of the user address space. There are two primary base integer variants, RV32I and RV64I. RISC-V has been designed to support extensive customization and specialization. The base integer ISA can be extended with one or more optional instruction-set extensions, but the base integer instructions cannot be redefined. Whereas other architectures usually treat their ISA as a single entity, which changes to a new version as instructions are added over time, RISC-V will endeavor to keep the base and each standard extension constant over time, and instead layer new instructions as further optional extensions.
  • Diversity Across Different Industries: RISC-V is making an impact in different industries and applications, such as automotive, aerospace, datacenter, IoT, AI and security applications. It is being used in systems where low power consumption and real-time processing are important.
  • Costs: reduced licensing costs with open-source nature and no proprietary ISA costs for implementing the RISC architecture

OPTIMIZATION OF AUDIO & VIDEO DECODING LIBRARIES

The goal is to support building and improve performance by optimizing critical functions using RISC-V assembly.

  • libhevc: Decoding of H.265/HEVC video streams, essential for multimedia playback and video processing applications.
  • libavc: Decoding of AVC/H.264 video streams, playing an integral role in multimedia playback and video processing applications.
  • libmpeg2: Decoding of MPEG-2 video streams, serving as a critical component in multimedia playback and diverse video processing tasks.
  • libxaac: Decoding of AAC (Advanced Audio Coding) audio streams, playing a pivotal role in various multimedia playback and audio processing applications.

Build support has been implemented for both Linux and Android, enabling the libraries to execute on a RISC-V platform using the original C code. For better performance, RISC-V assembly optimizations have been applied.

Strategy

Upon initial profiling of the libraries (original code) during decoding, time-critical functions were identified and chosen for optimization. The techniques that significantly optimized performance were loop unrolling, pipelining, and replacement of pseudo instructions with basic instructions.

 

Loop unrolling

A code transformation technique that replicates the body of a loop and reduces the number of iterations, thereby decreasing loop overhead and increasing opportunities to improve processor pipeline performance by reordering instructions.

Pipelining

A technique for implementing instruction-level parallelism within a single processor. It attempts to keep each part of the processor busy with some instruction. The technique presumes wise use of resources to optimize the RISC-V pipeline: instruction fetch, instruction decode and register fetch, execute, memory access, and register write-back.

Replacement of pseudo instructions with basic instructions

Further speeds up performance; pseudo instructions usually take more time to execute as they add an additional translation step.

Results

The execution time of the critical functions with our optimizations was measured (Android 14, VisionFive2 HW platform) and compared with the execution time of the original C code with the -O3 optimization flag. Multiple input audio/video files were used for the decoding process. The percentages achieved during optimization range from ~5% to ~40%.

The following graphs illustrate the results of optimization for specific functions and some of the input audio/video files.

Figure 1 libhevc optimization gains per function

Figure 2 libavc optimization gains per function

Figure 3 libmpeg2 optimization gains per function

The optimized code can be found on the Google Android Gerrit:

PORTING ANDROID 13

Porting Android 13 onto a RISC-V architecture-based development board requires a multifaceted approach, encompassing adaptations to the bootloader (u-boot), kernel configuration, and Android framework customization. Android 13 was ported onto the Starfive VisionFive2 board, equipped with the JH7110 processor.

Adapting the U-Boot Bootloader to Accommodate Android-Specific Requirements

By default, U-Boot is aimed at Debian systems and needs to be modified to support the booting of Android image components such as the kernel image (boot.img) and the ramdisk (init_boot.img and vendor_boot.img). U-Boot was extended to include support for the bootm command, enabling the sequential loading and execution of these image files. Through these modifications, it was established that U-Boot could handle Android boot images in accordance with the Android boot protocol.

Modification of Kernel Configuration to Enable Android Compatibility on the RISC-V Platform

This step includes integrating Android-specific features and services such as SELinux, binder, ashmem, bpfloader, and graphical drivers into the kernel framework. By configuring the kernel, integration with the Android ecosystem is ensured, laying the groundwork for subsequent functionalities. Additionally, support for bootconfig has been added. The bootconfig feature replaces the androidboot.* kernel command line. This feature provides a way to separate the configuration parameters for Android user-space from those for the kernel-space.

Android Framework Customization

The first step in Android framework customization was to create a specific Android device configuration for the VisionFive2 hardware platform. This involved configuring device-specific settings such as filesystem tables (fstab), initializing device-specific services, and changing system-level behaviors through init.rc scripts. Additionally, device-specific configuration files (Boardconfig and device.mk) were modified to ensure the integration of this hardware platform within the Android framework. These customizations enabled Android to boot successfully on the RISC-V development platform, initially with limited functionality—console functionality only.

The next steps involved further enabling functionalities, such as enabling graphical output by adding support for the graphics driver.

HYPERVISOR EXTENSION

Motivation

The growing popularity of RISC-V architecture urges support for virtualization technologies to enable the complete software ecosystem. Virtualization enables running of multiple domains with different operating systems (Linux, Android, QNX, etc.) on the same hardware platform. In terms of performance and security features, hypervisor as a bare-metal virtualization technology makes the best choice. Since a variety of Linux/Android distributions already include support for RISC-V architecture, open-source hypervisors developed by the community seem to be a solid candidate for RISC-V virtualization support.

Xen is a free open-source type-1 (bare-metal) hypervisor widely used for its scalability, rich toolset, and support for a wide range of architectures (ARM, Intel, PPC) and operating systems (Linux, Windows, Free BSD). Considering the advantages of Xen, it represents a great candidate for hypervisor deployment on RISC-V.

Status

Significant strides in extending Xen support for RISC-V architecture have been made by the community. While progress has been made, it remains in its nascent stages. The latest official Xen release (4.18) includes generating a minimal program image for RISC-V, without domain operating systems support. Although multiple supporting organizations have made some additional progress (e.g., XCP-ng has implemented support for Dom0 operating system), these updates have neither been included in the official Xen codebase, nor planned to be included in the upcoming release.

Several challenges are being faced in the process of extending Xen’s support for RISC-V architecture. These include:

  1. Limited functionality: The current state of Xen on RISC-V lacks many advanced features otherwise available on other architectures.
  2. Complexity of implementation: Adapting Xen’s codebase to suit the unique characteristics of RISC-V architecture requires meticulous effort and expertise.
  3. Community engagement: Encouraging wider participation and collaboration within the developer community is crucial for accelerating the pace of development.

Work in progress

In this early stage of Xen development for RISC-V, the focus is based on enabling the host, domain 0 operating system support and its extension with interfaces for guest operating system domains:

  • Dom0 operating system boot and initialization in Xen hypervisor environment
  • RISC-V MMU/IOMMU support
  • Xen toolset interfaces (interaction between Dom0 and Xen)
  • Dom0 (Linux) guest interface drivers’ implementation

Despite the challenges, the outlook for Xen on RISC-V is promising. With continued dedication from increased community involvement, it is expected that Xen’s support for RISC-V will evolve rapidly. As the ecosystem matures, we anticipate seeing broader adoption of Xen in RISC-V-based virtualization environments.

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