In the early days of FPGA design, validity of design was proven by downloading gate-level schematic design on a test board, and then validating the overall system functionality with real test data. Even with a smaller design with just a few thousand gates, it become clear that some form of simulation of the design will provide easier and faster method to resolve issues through early detection before downloading gate-level design on a test board.
With advancement of FPGA technology, more advanced design techniques were introduced, making the design more complex. This also led to advancement of verification methodologies such as eRM (e Reuse Methodology) for the e Verification Language, OVM (Open Verification Methodology) which is based on eRM, and UVM (Universal Verification Methodology), derived from OVM, for the SystemVerilog Language. All verification methodologies have the same goal to thoroughly check functionality of design before synthesis and physical testing.
eRM vs UVM overview
Today most commonly used methods of verification are eRM and UVM.
- eRM e Verification Language is Aspect-Oriented Programming (AOP) language used in conjunction with Specman tool from Cadence that provides advanced automated functional verification of hardware designs. Specman provides an environment for working with compiling and debugging testbench environments written in the e language. For design languages such as VHDL and Verilog, Specman tool itself doesn’t include simulator. To simulate an e-testbench with a design written in VHDL/Verilog, Specman must be run in conjunction with a separate HDL simulation tool (Simvision, Vmanager, CodeBeamer, Xcelium, etc).
- UVM is based on SystemVerilog Language which is Object Oriented Programming (OOP) language. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor Graphics, Synopsys, Xilinx Simulator (XSIM).
Here in RT-RK our team of verification engineers has worked on various verification projects for FPGA, ASIC and SoC designs using UVM System Verilog Language and eRM e Verification Language. Verification of every design was carefully planned and executed by RT-RK or in collaboration with the customer.
- Creating requirements and specification plan for verification
- Implementing eRM or UVM environment according to the requirements and specifications
- Implementing test procedures to verify functionality of the DUT (Design Under Test)
- 100% Code Coverage and 100% Requirement Coverage
- Generating report files to confirm validity of verification process and functionality of design
UVM Environment implementation
UVM environment consists of Agents, Predictors, and Scoreboards. Agent is via interface connected to the DUT, his purpose is to drive stimulus to DUT inputs and collect DUT output data for compare with expected data in scoreboard. Stimulus and expected values are created in tests. Example of UVM environment block diagram is shown in Figure 1.
Figure 1. UVM example environment
eRM environment implementation
eRM environment consists of Specman, Simvision and Test which applies and collects test data vectors. DUT is imported in Simvision simulation tool which is connected to Specman. Specman is responsible for generating stimulus according to the test inputs and collecting data from Simvision in order to check validity of DUT output data. Example of eRM environment is shown in Figure 2.
Figure 2. eRM example environment
All verification steps in projects were conducted or organized by RT-RK, in collaboration with customer. Requirements were fulfilled at an expected level. On the other side, RT-RK team has grown in knowledge on creating and maintaining verification environments and all the components included in multiple verification methodologies (eRM and UVM).