RISC-V BLOG

Your go-to hub for RISC-V topics direct from the minds of our top engineers in the field!

Deep dive into RISC-V GCC microarchitectures

RISC-V an open-source and modular instruction set architecture (ISA), has gained significant attention for its versatility in computing tasks anywhere from embedded to cloud environments. As RISC-V gains momentum in academia and industry, improving software support for RISC-V hardware becomes crucial for wider adoption. Understanding how the architecture interacts with compilers is the foundation for maximising performance.

In this series of articles we will do a deep dive into RISC-V microarchitectures, exploring how GCC, as one of the most popular compilers for RISC-V interacts with the underlying hardware to generate efficient machine code. The aim is to try and demystify what is the impact of microarchitecture features like pipelining, cache hierarchies, branch prediction and instruction scheduling and how GCC optimizes code to take full advantage of RISC-V’s modular design.