Introduction
The Serial Peripheral Interface (SPI) is a widely used data transfer protocol. With the growing demand for higher transfer speeds, newer versions of the SPI protocol—such as Dual SPI (DSPI) and Quad SPI (QSPI)—have been introduced to enable significantly faster data transmission. To meet these demands, we have developed a fully custom xSPI IP solution compliant with the Expanded Serial Peripheral Interface (xSPI) for Nonvolatile Memory Devices Standard (JESD251C).
Challenges
Developing the xSPI IP involves addressing several key challenges. It must be resource-efficient, user-friendly, and easily configurable, while also supporting a wide range of operating modes. In addition to standard SPI, the design supports Dual, Quad, and Octal SPI (OSPI) interfaces. Although the JESD251C specification formally defines only SPI and OSPI as valid operating modes, real-world implementations often deviate from this standard, making Dual and Quad SPI support equally important. In some cases, there is also a need to support mixed operating modes, which adds another layer of complexity. Ultimately, the product is intended to serve as a direct replacement for existing SPI, DSPI, and QSPI solutions.
Possible Approaches
- Memory-mapped implementation
- Support for JESD251C (SPI and OSPI operating modes)
- Support for SPI, DSPI, QSPI, and OSPI operating modes
- Support for SPI, DSPI, QSPI, OSPI, and mixed operating modes
The following sections elaborate on each approach and provide a comparison, which is summarized in the table below.
| Memory Mapped | JESD251C | JESD251C + DSPI and QSPI | JESD251C + DSPI and QSPI + Mixed operating modes | |
|---|---|---|---|---|
| Pros | Direct memory access without requiring knowledge of SPI transactions, resulting in shorter development time and faster time to market. | Allows the use of additional SPI commands defined by the JESD251C standard, but only in SPI and OSPI operating modes. | Enables the use of additional SPI commands defined by the JESD251C standard across SPI, DSPI, QSPI, and OSPI operating modes. | Enables the use of additional SPI commands defined by the JESD251C standard in SPI, DSPI, QSPI, and OSPI operating modes, as well as commands that utilize multiple operating modes within a single memory access. |
| Cons | SPI devices are not always fully compatible with one another, which may require adapting the solution. | Requires knowledge of SPI transactions. Does not support DSPI and QSPI operating modes. Does not support commands that utilize multiple operating modes within a single memory access. | Requires knowledge of SPI transactions. Does not support commands that utilize multiple operating modes within a single memory access. | Requires knowledge of SPI transactions. Significantly longer development time. |
Table 1. Overview of advantages and limitations of the possible approaches
Solution
The chosen solution supports SPI, DSPI, QSPI, OSPI, and mixed operating modes. The primary challenge was implementing all these modes while minimizing resource consumption. An additional challenge was developing a complete IP solution entirely with in-house resources, without requiring any additional licenses. A mechanism was implemented to allow users to easily submit commands and data to the IP. The communication format between the IP and the user is kept simple, while preserving the structure of the command transactions. The solution diagram is shown in Figure 1.
Figure 1. xSPI IP block diagram
Figure 1 shows the xSPI IP block diagram with all its interfaces. The Advanced eXtensible Interface (AXI) Lite slave interface is used for accessing xSPI IP status and configuration registers. AXI Stream master and slave interfaces handle data transfer between the host and the xSPI IP. The xSPI master interface manages data transfer between the xSPI IP and SPI slave devices. Internal buffers are included on the AXI Stream master and slave interfaces, and their sizes can be adjusted by the user if needed.
Results and Future Improvements
The hardware implementation of the xSPI IP was performed on a CRUVI CR00107 Base Board equipped with an AMD Spartan-7 Field Programmable Gate Array (FPGA) and EVERSPIN EMxxLX Spin-Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM).
Figure 2. CRUVI CR00107 Base Board with the EVERSPIN MRAM Daughter board
MRAM leverages magnetic states rather than electrical charges to store data, enabling the production of non-volatile memory (NVM) chips that operate at speeds typically associated with RAM. This combines the persistent storage of flash memory with the speed and resilience of RAM. It also eliminates the need for backup power sources such as batteries or capacitors, making MRAM particularly suitable for devices that must function reliably in critical environments.
MRAM’s standard interfaces, both parallel and serial, allow for seamless integration, offering low-latency storage and retrieval. Everspin has recently introduced the xSPI PERSYST MRAM product family, based on the Expanded Serial Peripheral Interface (xSPI), the latest JEDEC standard for non-volatile memory devices. Built on Everspin's industrial STT-MRAM technology, these products offer high performance, multiple I/O support, SPI compatibility, and a high-speed, low-pin-count SPI-compatible bus interface with clock frequencies up to 200 MHz.
These persistent MRAM devices operate on a single 1.8 V power supply and deliver up to 400 MBps for both reads and writes via eight I/O signals. This advancement ushers in a new era of universal memory solutions, replacing products such as SRAM, BBSRAM, NVSRAM, and NOR devices, and targeting Industrial Automation, Process Control, Emulation, Automotive and Transportation, Gaming, and the broader Industrial Internet of Things (IIoT) markets.
The xSPI IP implementation was carried out using the AMD Vivado development tool. An AMD MicroBlaze soft-core Central Processing Unit (CPU) was used to configure the xSPI IP. Bare-metal testing was performed using the Vitis Integrated Design Environment (IDE). Table 2 shows the achieved read/write speeds for each operating mode on the implemented solution.
| SPI | Dual SPI | Quad SPI | Octal SPI | |||
|---|---|---|---|---|---|---|
| Data Rate | Single | Single | Single | Double | Single | Double |
| Bandwidth (Mbps) | Up to 50 | Up to 100 | Up to 200 | Up to 400 | Up to 400 | Up to 800 |
Table 2. Read/write bandwidth of AMD Spartan-7 with EVERSPIN EMxxLX MRAM
Due to the speed limitations of the AMD Spartan-7, only 800 Mbps bandwidth was achieved using a 50 MHz xSPI clock. Higher bandwidth can be attained by porting the IP to a faster FPGA device.
The xSPI IP has been designed to allow straightforward adaptation to other FPGA development platforms. Future improvements include porting the xSPI IP to other AMD FPGA families as well as to devices from other vendors, such as Lattice and Altera.
Currently, the xSPI IP supports only a single device. Future versions could enable support for multiple xSPI slave devices.
To ensure robustness and correctness, the Universal Verification Methodology (UVM) was used for verification in a simulation environment.
Conclusion
The xSPI IP core delivers a highly flexible direct-replacement solution, supporting multiple operating modes including SPI, DSPI, QSPI, OSPI, and mixed modes to ensure broad compatibility with serial peripheral devices. Designed entirely in-house, the IP is robust, highly configurable, and resource-efficient, eliminating the need for third-party IP licenses. Its implementation on an AMD Spartan-7 FPGA with a MicroBlaze CPU and successful testing with Everspin EMxxLX STT-MRAM confirmed high-speed performance and straightforward integration. Planned future enhancements will further increase adaptability, making the xSPI IP suitable for a wide range of market applications.